1. Field of the Invention
This invention relates generally to the shared usage of memory by a plurality of agents, i.e., processors. In particular, it relates to the synchronization of a clock signal to shared synchronous memory using an arbiter-controlled switched clock.
2. Background of Related Art
With the ever-increasing speeds of today's processors, memory designs have attempted to meet the required speed requirements. For instance, synchronous memory such as synchronous static random access memory (SSRAM) and synchronous dynamic random access memory (SDRAM) are commonly available synchronous types of memory.
Synchronous memory technology is currently used in a wide variety of applications to close the gap between the needs of high-speed processors and the access time of asynchronous memory such as dynamic random access memory (DRAM). Synchronous memory, e.g., SDRAM technology, combines industry advances in fast dynamic random access memory (DRAM) with a high-speed interface.
Functionally, an SDRAM resembles a conventional DRAM, i.e., it is dynamic and must be refreshed. However, the DRAM architecture has improvements over standard DRAMs. For instance, an SDRAM uses internal pipelining to improve throughput and on-chip interleaving between separate memory banks to eliminate gaps in output data.
The idea of using an SDRAM synchronously (as opposed to using a DRAM asynchronously) emerged in light of increasing data transfer demands of high-end processors. SDRAM circuit designs are based on state machine operation instead of being level/pulse width driven as in conventional asynchronous memory devices. Instead, the inputs are latched by the system clock. Since all timing is based on the same synchronous clock, designers can achieve better specification margins. Moreover, since the SDRAM access is programmable, designers can improve bus utilization because the processor can be synchronized to the SDRAM output.
The core of an SDRAM device is a standard DRAM with the important addition of synchronous control logic. By synchronizing all address, data and control signals with a single clock signal, SDRAM technology enhances performance, simplifies design and provides faster data transfer.
Similar advantages hold for other types of synchronous memory, e.g., SSRAM or even synchronous read only memory.
Synchronous memory requires a clock signal from the accessing agent to allow fully synchronous operation with respect to the accessing agent.
For example, FIG. 3 shows a prior art system including one agent 300 and a synchronous memory 302, e.g., SRAM. The agent 300 communicates with the synchronous memory 312 using appropriate address, data and control buses (ADC) 306, and a clock signal 304. Because the synchronous memory 302 has only one accessing agent 300, the synchronous memory 302 need only contend with one clock signal 304.
Conventional synchronous memory systems utilize only a single agent. If more than one agent were to be given access to a shared synchronous memory, each agent must supply its own clock signal to the synchronous memory. Unfortunately, the clock signals from separate agents are typically not synchronous or in phase with one another, and thus conventional synchronous memory systems are not shared among a plurality of agents, without using an asynchronous interface, which may be prone to glitches and/or race conditions. This is potentially wasteful of memory in systems having a plurality of agents because the memory must be sized for a maximum potential application for each agent.
Moreover, undesirable conditions would result from the potential for interruption and/or incomplete address, data and/or control access to the shared synchronous memory. For instance, transitional changes of address, data and/or control signals could cause damage to memory cells, unwanted write operations to certain memory cells, and/or unwanted read operations causing the appearance of data on an output data bus of the shared synchronous memory shared with the output data bus of other shared synchronous memory resulting in short circuits on the output data bus.
There is thus a need for a system which is capable of sharing synchronous memory among a plurality of agents.